Difference between revisions of "User:Mxberner"
From REU@MU
| Line 15: | Line 15: | ||
- Exploring CS | - Exploring CS | ||
- Virgil Programming Language | - Virgil Programming Language | ||
| − | - RISC-V | + | - RISC-V Architecture |
- Researched RISC-V as a potential processor to port OS Xinu over to. | - Researched RISC-V as a potential processor to port OS Xinu over to. | ||
| Line 21: | Line 21: | ||
'''6/1''' | '''6/1''' | ||
| + | Further research into RISC-V | ||
| + | |||
| + | - RISC refers to Reduced Instruction Set Computer | ||
| + | - Advantage: Open-Source license that does not require fees to use (and therefore it tends to be cheaper). Creating a custom chip is easier as well. | ||
| + | - Advantage: Base module has only integer registers. The very limited modules allow for customization and optimization | ||
| + | - Advantage: Power efficient, magnitudes less energy than CISC models. Has the ability to turn off individual cores and parallel compute. | ||
| + | - Disadvantage: Not many purchasable, brand-name RISC-V processors available. The market is flooded with less trustworthy options at its current state. | ||
| + | - Disadvantage: With only simple instructions available, complex tasks (i.e. video editing) are much slower with only RISC-V architecture. (This does allow for a higher core-density in a physical chip though). | ||
Revision as of 16:50, 3 June 2022
Max Berner Marquette REU Summer 2022 Advisor: Dr. Brylow
5/31 Orientation Day
- Met the cohort, mentor, and research group.
- Reviewed potential subjects of research
- Exploring CS - Virgil Programming Language - RISC-V Architecture
- Researched RISC-V as a potential processor to port OS Xinu over to.
6/1
Further research into RISC-V
- RISC refers to Reduced Instruction Set Computer - Advantage: Open-Source license that does not require fees to use (and therefore it tends to be cheaper). Creating a custom chip is easier as well. - Advantage: Base module has only integer registers. The very limited modules allow for customization and optimization - Advantage: Power efficient, magnitudes less energy than CISC models. Has the ability to turn off individual cores and parallel compute. - Disadvantage: Not many purchasable, brand-name RISC-V processors available. The market is flooded with less trustworthy options at its current state. - Disadvantage: With only simple instructions available, complex tasks (i.e. video editing) are much slower with only RISC-V architecture. (This does allow for a higher core-density in a physical chip though).
