Difference between revisions of "User:Mxberner"
From REU@MU
(→=) |
|||
| Line 31: | Line 31: | ||
- Disadvantage: Not many purchasable, brand-name RISC-V processors available. | - Disadvantage: Not many purchasable, brand-name RISC-V processors available. | ||
- Disadvantage: With only simple instructions available, complex tasks are slower. | - Disadvantage: With only simple instructions available, complex tasks are slower. | ||
| + | |||
| + | ================================================================================================= | ||
Revision as of 16:57, 3 June 2022
Max Berner Marquette REU Summer 2022 Advisor: Dr. Brylow
5/31 Orientation Day
- Met the cohort, mentor, and research group.
- Reviewed potential subjects of research
- Exploring CS - Virgil Programming Language - RISC-V Architecture
- Researched RISC-V as a potential processor to port OS Xinu over to.
=====================================================================================
6/1 Further research into RISC-V
- RISC refers to Reduced Instruction Set Computer - Advantage: Open-Source license that does not require fees to use - Advantage: Creating a custom chip is easier - Advantage: Base module is extremely limited, allowing customization/optimization. - Advantage: Power efficient, magnitudes less energy than CISC models. - Disadvantage: Not many purchasable, brand-name RISC-V processors available. - Disadvantage: With only simple instructions available, complex tasks are slower.
