Difference between revisions of "User:Mxberner"

Revision as of 23:09, 7 June 2022

Max Berner

Marquette REU Summer 2022

Advisor: Dr. Brylow

Weekly Logs

Week 1 (05/31/22 - 06/05/21)

• Met the cohort, mentor, and research group.
• Reviewed potential subjects of research

 - Updating Exploring CS curriculum
 - Porting Embedded XINU to Virgil Programming Language
 - Porting Embedded XINU to RISC-V Architecture

• Researched RISC-V as a potential processor to port OS Xinu over to.

=====================================================================================

6/1 Further research into RISC-V

- RISC-V is most applicable for small devices with it's energy conservation and great performance for strictly simple tasks.

 - RISC refers to Reduced Instruction Set Computer
 - Advantage: Open-Source license that does not require fees to use
 - Advantage: Creating a custom chip is easier
 - Advantage: Base module is extremely limited, allowing customization/optimization.
 - Advantage: Power efficient, magnitudes less energy than CISC models. 
 - Disadvantage: Not many purchasable, brand-name RISC-V processors available. 
 - Disadvantage: With only simple instructions available, complex tasks are slower.

- Conducted personal research into single-board computers, hardware architecture, and assembly language to contextualize my research of RISC-V.

=====================================================================================

5/31 Virgil and RCR

- Completed RCR training modules through CITI program