Difference between revisions of "User:Blevando"
From REU@MU
(→Work log) |
|||
| (7 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | I am an undergraduate at [http://valpo.edu Valparaiso University] pursuing a Bachelor of Science in Computer Science. | ||
| + | |||
E-mail: benjamin.levandowski@marquette.edu | E-mail: benjamin.levandowski@marquette.edu | ||
| − | |||
== Work log == | == Work log == | ||
| Line 11: | Line 12: | ||
** Paper on MiniOS and Papers on the Tock Embedded OS | ** Paper on MiniOS and Papers on the Tock Embedded OS | ||
** Paper describing Xest | ** Paper describing Xest | ||
| + | ** Looked at the ARM Cortex-A53 Technical Reference Manual to familiarize myself with ARM assembly and C calling convention | ||
** Skimmed papers on Computer Science Secondary Education | ** Skimmed papers on Computer Science Secondary Education | ||
* Began to familiarize myself with Embedded Xinu by completing the UART homework from COSC 3250 | * Began to familiarize myself with Embedded Xinu by completing the UART homework from COSC 3250 | ||
* Briefly explored the Rust programming language | * Briefly explored the Rust programming language | ||
| + | * Finalized a research project | ||
| + | |||
| + | '''Week 2''' | ||
| + | * Read through relevant portions of the [https://dl.acm.org/citation.cfm?id=2534860 ACM/IEEE Computer Science Curricula 2013 Report] | ||
| + | * Found and read papers relating to computer science education in parallel and distributed computing and its relation to hardware | ||
| + | ** Primarily searched through publications that derived from the Special Interest Group in Computer Science Education | ||
| + | * Furthered my familiarity with the multi-core Pi 3 | ||
| + | * Learned more ARM assembly by exploring the factorial homework from COSC 2200 | ||
| + | * Learned how not to give a presentation | ||
| + | * Began to build a sandbox environment for XINU PI3 to mirror the arm playground for the Raspberry Pi | ||
| + | ** Successfully able to run an isolated assembly file on the Pi3 | ||
| + | ** Environment still needs better structure | ||
| + | ** Need to be able to easily run code on all cores | ||
| + | |||
| + | '''Week 3''' | ||
| + | * Sandbox environment easily runs code on all processors | ||
| + | ** Behavior is unpredictable after code terminates, loop forever for now | ||
| + | * Completed Responsible Conduct of Research training including online modules and face-to-face discussion | ||
| + | * Searched for programming tasks used in education | ||
| + | ** Tasks designed for parallel assembly elude me, but some may be able to be modified to fit this purpose | ||
| + | * Serial output needs attention now that up to 4 cores may write to it at once | ||
| + | * A specific teachable task will be chosen next week | ||
| + | |||
| + | '''Week 4''' | ||
| + | * Decided on a specific problem, the coupon collector's problem | ||
| + | ** Easy to parallelize, works naturally with shared memory, and fits well with existing curricula | ||
| + | * Implemented single core version in ARM assembly | ||
| + | * Extended functionality to multi-core | ||
| + | * Began to use mutexes and made use of atomic assembly instructions | ||
| + | * Program does not yet work properly; either there exists race conditions or issue with cache coherence | ||
| + | * Continued to debug software and explored solutions presented online | ||
| + | |||
| + | '''Week 5''' | ||
| + | * Changed memory attributes to fix existing issues with cache | ||
| + | * Can now demonstrate existence of race conditions | ||
| + | * Continued to read through ARM documentation to better understand the ISA | ||
| + | * Presented first five weeks' work to peers and faculty | ||
| + | * Looked over NEON advanced SIMD documentation | ||
| + | * Continued to adjust the memory model and MMU setup | ||
| + | |||
| + | '''Week 6''' | ||
| + | * Isolated memory issues in program | ||
| + | ** Can now demonstrate 2 types of memory/cache problems caused by sharing memory among cores | ||
| + | * Re-wrote MMU initialization function in assembly to follow the ARM bare metal example | ||
| + | ** This makes setting up the memory translation table more transparent | ||
| + | * Redesigned reserved space sharing setup to improve readability | ||
| + | * Improved function termination strategy—Core 0 no longer has to guess if other cores are still running | ||
| + | * Attempted implementing a semaphore for the PRNG use, though this largely negates the purpose of running on multiple cores | ||
| + | ** I may just have each core have its own PRNG | ||
| + | * Next week will focus on curricular material and improving formal documentation | ||
| + | |||
| + | '''Week 7''' | ||
| + | * Met with professor Perouli to discuss plans for the fall semester | ||
| + | * Read up on ARM's support for Advanced SIMD operations and vector instructions | ||
| + | * Completed example code for a distributed memory model for comparisons | ||
| + | ** Makes use of vector operations when combining results. | ||
Latest revision as of 21:23, 27 July 2018
I am an undergraduate at Valparaiso University pursuing a Bachelor of Science in Computer Science.
E-mail: benjamin.levandowski@marquette.edu
Work log
Week 1
- General Orientation of REU and projects, along with Marquette University and its facilities
- Met with mentor and student researchers to discuss potential projects
- Read literature regarding potential projects
- Previous summer's research paper and an older paper on Embedded Xinu
- Paper on MiniOS and Papers on the Tock Embedded OS
- Paper describing Xest
- Looked at the ARM Cortex-A53 Technical Reference Manual to familiarize myself with ARM assembly and C calling convention
- Skimmed papers on Computer Science Secondary Education
- Began to familiarize myself with Embedded Xinu by completing the UART homework from COSC 3250
- Briefly explored the Rust programming language
- Finalized a research project
Week 2
- Read through relevant portions of the ACM/IEEE Computer Science Curricula 2013 Report
- Found and read papers relating to computer science education in parallel and distributed computing and its relation to hardware
- Primarily searched through publications that derived from the Special Interest Group in Computer Science Education
- Furthered my familiarity with the multi-core Pi 3
- Learned more ARM assembly by exploring the factorial homework from COSC 2200
- Learned how not to give a presentation
- Began to build a sandbox environment for XINU PI3 to mirror the arm playground for the Raspberry Pi
- Successfully able to run an isolated assembly file on the Pi3
- Environment still needs better structure
- Need to be able to easily run code on all cores
Week 3
- Sandbox environment easily runs code on all processors
- Behavior is unpredictable after code terminates, loop forever for now
- Completed Responsible Conduct of Research training including online modules and face-to-face discussion
- Searched for programming tasks used in education
- Tasks designed for parallel assembly elude me, but some may be able to be modified to fit this purpose
- Serial output needs attention now that up to 4 cores may write to it at once
- A specific teachable task will be chosen next week
Week 4
- Decided on a specific problem, the coupon collector's problem
- Easy to parallelize, works naturally with shared memory, and fits well with existing curricula
- Implemented single core version in ARM assembly
- Extended functionality to multi-core
- Began to use mutexes and made use of atomic assembly instructions
- Program does not yet work properly; either there exists race conditions or issue with cache coherence
- Continued to debug software and explored solutions presented online
Week 5
- Changed memory attributes to fix existing issues with cache
- Can now demonstrate existence of race conditions
- Continued to read through ARM documentation to better understand the ISA
- Presented first five weeks' work to peers and faculty
- Looked over NEON advanced SIMD documentation
- Continued to adjust the memory model and MMU setup
Week 6
- Isolated memory issues in program
- Can now demonstrate 2 types of memory/cache problems caused by sharing memory among cores
- Re-wrote MMU initialization function in assembly to follow the ARM bare metal example
- This makes setting up the memory translation table more transparent
- Redesigned reserved space sharing setup to improve readability
- Improved function termination strategy—Core 0 no longer has to guess if other cores are still running
- Attempted implementing a semaphore for the PRNG use, though this largely negates the purpose of running on multiple cores
- I may just have each core have its own PRNG
- Next week will focus on curricular material and improving formal documentation
Week 7
- Met with professor Perouli to discuss plans for the fall semester
- Read up on ARM's support for Advanced SIMD operations and vector instructions
- Completed example code for a distributed memory model for comparisons
- Makes use of vector operations when combining results.
