Difference between revisions of "User:Mxberner"

Revision as of 20:05, 9 June 2022

Max Berner

Marquette REU Summer 2022

Advisor: Dr. Brylow

Summer 2022 Project: https://reu.cs.mu.edu/index.php/Porting_Embedded_XINU_to_Virgil

Weekly Logs

Week 1 (05/31/22 - 06/05/22)

• Met the cohort, mentor, and research group.
• Reviewed potential subjects of research

 - Updating Exploring CS curriculum
 - Porting Embedded XINU to Virgil Programming Language
 - Porting Embedded XINU to RISC-V Architecture

• Researched RISC-V as a potential processor to port OS Xinu over to.

 - RISC-V is most applicable for small devices with it's energy conservation and great performance for strictly simple tasks.
 - RISC refers to Reduced Instruction Set Computer
 - Advantage: Open-Source license that does not require fees to use
 - Advantage: Creating a custom chip is easier
 - Advantage: Base module is extremely limited, allowing customization/optimization.
 - Advantage: Power efficient, magnitudes less energy than CISC models. 
 - Disadvantage: Not many purchasable, brand-name RISC-V processors available. 
 - Disadvantage: With only simple instructions available, complex tasks are slower.

• Conducted personal research into single-board computers, hardware architecture, and assembly language to contextualize my research of RISC-V.
• Completed online RCR training modules through CITI program
• Began research into Virgil

Week 2 (06/06/22 - 06/12/22)

• Completed in-person RCR training
• Created wiki page for Porting Embedded XINU to Virgil Programming Language.
• Began contextual research into porting and operating systems.
• Attended technical writing presentation
• Installed and set-up Debian, a Linux environment on my Windows computer through WSL. (Required since Virgil does not compile to Windows)
• Executed a "Hello World!" written in Virgil on Debian
• Established remote connection to @morbius.mscs.mu.edu.
• Cloned Embedded Xinu and Virgil repositories to morbius.