Difference between revisions of "Porting Embedded XINU to RISC-V"

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(Created page with "'''Students:''' Alex Gebhard, Jack Forden <br/> '''Mentor:''' [https://cs.mu.edu/~brylow Dr. Dennis Brylow] == Project Background == Embedd...")
 
(→‎Tentative Milestones)
 
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== Project Description ==
 
== Project Description ==
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With the rise of RISC-V, we are hoping to port the current version of XINU to the RISC-V architecture.   
+
With the rise of RISC-V, we will port the current version of Embedded XINU to the RISC-V architecture.  RISC-V is a license-free RISC ISA that is maintained by the non-profit RISC-V Foundation.  RISC-V is designed to be simple, yet customizable. RISC-V was originally a project at the University of California Berkeley.  Once we complete the port to RISC-V, we plan on rolling it out to classes such as COSC 3250: Operating Systems, COSC 3410: Programming Languages, COSC 4300: Networking, and COSC 4400 Compilers.
  
 
== Tentative Milestones ==
 
== Tentative Milestones ==
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*Create a bootable operating system that can output to a UART
 
*Create a bootable operating system that can output to a UART
 
*Research interrupts and interrupt handlers on RISC-V
 
*Research interrupts and interrupt handlers on RISC-V
 +
*Implement processes and context switch
 +
|-
 +
|Week 3
 +
|
 +
*Implement supervisor mode.  Switch processes to run in user mode
 +
*Implement system calls for user_yield, user_printf, and user_none
 +
|-
 +
|Week 4
 +
|
 +
*Discuss ideal model for process scheduling
 +
*Implement process scheduling
 +
*Implement process accounting
 +
*Begin work on mid-summer presentation
 +
|-
 +
|Week 5
 +
|
 +
*Research requirements to implement paging
 +
*Add memory protection for kernel pages to prevent writing
 +
*Begin paging implementation for XINU
 +
*Present REU mid-summer presentation
 +
|-
 +
|Week 6
 +
|
 +
*Implement Pthreads API
 +
*Research how to load ELF files
 +
*Begin writing ELF loader
 +
|-
 +
|Week 7
 +
|
 +
*Finish ELF loader
 +
*Begin adding device layer to RISC-V implementation
 +
*Review device layer to ensure it supports multicore
 +
|-
 +
|Week 8
 +
|
 +
*Finalize device layer
 +
*Add interactive shell to XINU
 +
*Preform code review of summer work
 +
*Update XINU wiki
 +
|-
 +
|Week 9
 +
|
 +
*Begin writing research paper
 +
*Start final REU presentation
 +
*Design and review poster
 +
|-
 +
|Week 10
 +
|
 +
*Finalize REU paper
 +
*Present poster
 +
*Present final REU presentation
 
|}
 
|}

Latest revision as of 16:05, 15 June 2022

Students: Alex Gebhard, Jack Forden
Mentor: Dr. Dennis Brylow

Project Background

Embedded Xinu is a lightweight research and teaching based operating system designed for simplicity. Embedded Xinu is used to teach multiple undergraduate and graduate classes at Marquette University such as COSC 3250: Operating Systems, COSC 2200: Hardware Systems, and COSC 4300: Networks and Internets. Embedded Xinu is based off the Xinu operating system developed by Douglas Comer. Work on Embedded Xinu began in the summer of 2006 to support the MIPS based platform. Currently, Embedded Xinu supports Linksys WRT54GL, Linksys WRT160NL, as well as the Qemu-mipsel virtual machine. In 2013, Embedded Xinu was ported to the Raspberry Pi 1 B+, called XinuPi. This was the first port to the ARM architecture. The Raspberry Pi 1 B+ is a single core Broadcom BCM2835 SoC with 512 megabytes of RAM. In 2018, the Raspberry Pi 3 B+ was released. Unlike the Raspberry Pi 1 B+, the Raspberry Pi 3 B+ has a multicore Broadcom BCM2837B0 SoC with 1 gigabyte of RAM. There is currently a stable port of Embedded Xinu to the multicore Raspberry Pi 3B+, called XinuPi3.

Project Description

With the rise of RISC-V, we will port the current version of Embedded XINU to the RISC-V architecture. RISC-V is a license-free RISC ISA that is maintained by the non-profit RISC-V Foundation. RISC-V is designed to be simple, yet customizable. RISC-V was originally a project at the University of California Berkeley. Once we complete the port to RISC-V, we plan on rolling it out to classes such as COSC 3250: Operating Systems, COSC 3410: Programming Languages, COSC 4300: Networking, and COSC 4400 Compilers.

Tentative Milestones

Week Description
Week 1
  • Meet with project leaders, mentor, and other students
  • Set milestones and goals for the project duration
  • Discuss project with Dr. Dennis Brylow
Week 2
  • Create a bootable operating system that can output to a UART
  • Research interrupts and interrupt handlers on RISC-V
  • Implement processes and context switch
Week 3
  • Implement supervisor mode. Switch processes to run in user mode
  • Implement system calls for user_yield, user_printf, and user_none
Week 4
  • Discuss ideal model for process scheduling
  • Implement process scheduling
  • Implement process accounting
  • Begin work on mid-summer presentation
Week 5
  • Research requirements to implement paging
  • Add memory protection for kernel pages to prevent writing
  • Begin paging implementation for XINU
  • Present REU mid-summer presentation
Week 6
  • Implement Pthreads API
  • Research how to load ELF files
  • Begin writing ELF loader
Week 7
  • Finish ELF loader
  • Begin adding device layer to RISC-V implementation
  • Review device layer to ensure it supports multicore
Week 8
  • Finalize device layer
  • Add interactive shell to XINU
  • Preform code review of summer work
  • Update XINU wiki
Week 9
  • Begin writing research paper
  • Start final REU presentation
  • Design and review poster
Week 10
  • Finalize REU paper
  • Present poster
  • Present final REU presentation
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